This application claims the priority of Japanese Patent application Nos. 4-20312 filed Feb. 5, 1992, 4-43958 filed Feb. 28, 1992, 4-58440 filed Mar. 16, 1992 and 4-64147 filed Mar. 19, 1992.
1. Field of the Invention
The present invention relates to a product-sum operation unit included in a variety of processors.
Due to the requirement for high speed operation of computer sytems in recent years, arithmetic operations, particularly high speed product-sum operation is in a high demand. Product-sum operation means the addition of the multiplication result of two numbers (multiplicand and multiplier), to another number (addend). This product-sum operation is an indispensable arithmetic operation for processing, for example, a digital output signal from an analog-to-digital converter. Namely, the product-sum operation is an indispensable arithmetic operation for realizing, for example, the filtering process of a modem (modulator-demodulator) comprising and analog-to-digital converter, or high speed servo control, for the positioning of the read head in a hard disk driver.
Owing to the progress of semiconductor technology in recent years, a high performance product-sum operation unit included in a digital signal processor (DSP) or a micro-controller, etc. As explained above, a product-sum operation unit is now an indispensable element for realizing a variety of communication equipment or high performance control equipment.
2. Description of the Related Art
As a product-sum operation unit, a digital multiplication cumulative adder unit has been proposed in the Japanese Unexamined Laid-Open Provisional Publication SHO 59-194242. This digital multiplication cumulative adder unit is formed by three or four multiplying units, first and second adders, first and second registers and a plurality of multiplexers. Each multiplying unit calculates each partial product by multiplying each partial data of a multiplicand and each partial data of a multiplier. The first and second adders generate a product by adding such partial products. The first register stores the resulting products. The second adder cumulatively adds the values of the first and second registers, and the second register stores the result of such additions. While the second adder cumulatively adds the values of the first and second registers, each multiplying unit calculates the partial products of the multiplicands and multipliers. The first and second adders generate a product by adding the new partial products. The first register stores the resulting products. The second adder cumulative adds the values of first and second registers and the second register stores the result of the addition.
As explained above, a digital multiplication cumulative adder unit realizes high speed multiplication cumulative addition, namely a product-sum operation by introducing a strategic hardware configuration.
However, the product-sum operation of this digital multiplication cumulative adder unit considers the cumulative result, which is stored in the second register, as an addend. Therefore, this digital multiplication cumulative adder unit cannot execute a product-sum operation using a desired number as an addend, and operations other than the product-sum operation, such as the continuous addition of two desired numbers. Therefore, when it is required to form a digital signal processor or microcontroller, etc., by loading this digital multiplication cumulative adder unit, another arithmetic unit which can execute operations other than the product-sum operation is also required. Accordingly, there rises a problem that it is impossible to realize integration of digital signal processor or microcontroller, etc.
A product-sum operation unit for executing a product-sum operation through program control has also been proposed. FIG. 41 illustrates a block diagram of a product-sum operation unit 200, for executing a product-sum operation, with two instructions, a multiplication instruction and an addition instruction. This product-sum operation unit 200 is formed by an instruction register 201, an instruction decoder 202, a multiplying unit 203, a pipeline register 204, a data selector 205 and an adder unit (hereinafter, referred to as ALU) 206. The pipeline register 204 is provided for realizing high speed product-sum operation.
This product-sum operation unit 200 uses a multiplication instruction "C.times.D .fwdarw.P" and an addition instruction "P+A .fwdarw.A". The multiplication instruction "C.times.D .fwdarw.P" is used for storing a product of a multiplicand C and a multiplier D in the pipeline register 204. The addition instruction "P+A .fwdarw.A" is used for adding a value stored in the pipeline register 204, namely the multiplication result of the multiplying unit 203, and a number A, and for assigning the resulting sum to the new number A.
As shown in FIG. 42, when the multiplication instruction "C.times.D .fwdarw.P" is loaded in an instruction register 201 during the first machine cycle Tc1, this multiplication instruction "C.times.D .fwdarw.P" is decoded into a control signal by the instruction decoder 202. This control signal is outputted to the multiplying unit 203. On the basis of this control signal, the multiplying unit 203 executes the multiplication, and outputs the multiplication result to the pipeline register 204. This multiplication result is loaded into the pipeline register 204 during the next machine cycle Tc2.
When the addition instruction "P+A .fwdarw.A" is loaded into the instruction register 201 during the next machine cycle, this addition instruction "P+A .fwdarw.A" is decoded into a control signal by the instruction decoder 202. This control signal is outputted to the selector 205. On the basis of this control signal, the multiplication result is selected via the pipeline register 204, by the data selector 205.
Thereafter, the addition of the multiplication result and the number A is executed by ALU 206, based on the control signal from the instruction decoder 202. The addition result is the desired product-sum, and is used as a new number A to be added.
However, when a programmer generates a program for executing the product-sum operation, using the product-sum operation unit 200 shown in FIG. 41, with the generation of a program consisting of the multiplication instruction and addition instruction, etc., to recognize the operation of the pipeline register 204, namely recognition of the fact that the desired multiplication result has been stored or not, is required. Namely, as shown in FIG. 42, it must be recognized that a value of the pipeline register 204 of the addition instruction "P+A .fwdarw.A", that is loaded into the instruction register 201 during the machine cycle Tc2, uses a value of the pipeline register 204 of the multiplication instruction "C.times.D .fwdarw.P", that is loaded into the instruction register 201 during the first machine cycle Tc1. Moreover, in the case of loading the multiplication and addition instructions "C.times.D .fwdarw.P, P+A .fwdarw.A" to the instruction register 201 during the machine cycle Tc3, it must be recognized that a value of the pipeline register 204 of the addition instruction "P+A .fwdarw.A" must be a value of the pipeline register 204 of the multiplication instruction "C.times.D .fwdarw.P", that is loaded into the instruction register 201, during the machine cycle Tc2. As explained above, there lies a problem that the generation of a program to operate the product-sum operation unit 200 is a large load for a programmer.
In addition, this product-sum operation unit 200 requires two machine cycles Tc1, Tc2 in order to generate only a result of the product-sum operation, thus causing a problem in the processing speed.